A recent CD (Compact Disk) player is capable of normal-speed playback when reading audio data from a CD, and 32X-speed playback when reading computer data from a CD. In such a CD player capable of playing both of a CD containing audio data and a CD containing computer data, when playing the disk at 32X speed, the maximum frequency of the reproduced data pulse read from the disk of the reproduced data pulse read from the disk becomes 32 times as high as that at the normal-speed playback and, therefore, the frequency of a clock generated in phase-synchronization with the reproduced data also becomes 32 times as high as that at the normal-speed playback. That is, the frequency bands of clocks handled by one CD player extend widely.
Further, in the CD player capable of the high-speed playback mentioned above, there is a difference in the maximum frequency components of the reproduced data pulses between playback of data recorded on the inner radius of the disk and playback of data recorded on the outer radius of the disk.
For this reason, the range of frequencies oscillated by a VCO (Voltage Controlled Oscillator), which is provided in a PLL circuit for generating a clock to read disk data, is also wide.
Accordingly, a PLL circuit included in the CD player having the above-mentioned high-speed playback function is required to quickly respond to a wide range of frequency bands handled in the CD player, and conventionally, a PLL circuit provided with a frequency comparator is employed to meet this requirement. FIG. 3 shows a PLL circuit provided with a frequency comparator (hereinafter referred to as “PLL circuit X”).
The conventional PLL circuit X comprises a frequency comparator 1, a phase comparator 2, a first charge pump 4, and second charge pump 5, a loop filter 6 and a VCO 7.
The frequency comparator 1 included in the conventional PLL circuit X brings a clock generated by the VCO 7 up to a range where the phase comparator 2 can synchronize the phase of the reproduced data pulse and the phase of the clock generated by the VCO 7, i.e., a range where the phase comparator 2 can lock the phases. Once the phases are locked, the clock generated by the VCO 7 is prevented from being adversely affected by the output of the frequency comparator, using a signal to the half the operation of the frequency comparator 1.
In the aforementioned PLL circuit X, however, since the range of adaptable frequency bands is broad, fluctuations in the output from the first charge pump 4 for controlling the VCO 7 according to the output of the frequency comparator 1 are increased, whereby the range of fluctuations in the output from the loop filter 6 for smoothing the output of the first charge pump 4 becomes wide, resulting in an unstable PLL circuit.
To be specific, the frequency of the clock generated by the VCO 7 changes in proportion with the output voltage of the loop filter 6. So, in order to bring the clock generated by the VCO 7 into phase-synchronization with the reproduced data pulse quickly, the frequency of the clock generated by the VCO 7 must be increased or decreased quickly in a stroke.
Furthermore, when the reproduced data pulse has a large amount of jitter, the frequency comparator 1 generates jitters in the clock generated by the VCO 7 in response to the clock jitters of the reproduced data pulse. As the result, the phase comparator 2 cannot lock the phases.